Development of semiconductor memory devices has continuously improved with respect to operating speed and integration rate. A single data rate synchronous dynamic random access memory (hereinafter, referred to SDR SDRAM) was proposed to increase the operating speed. The SDR SDRAM inputs or outputs one of the data through a data pin during one period of an external clock, particularly in synchronization with a rising edge of the external clock. However, the SDR SDRAM is insufficient for a system operating at higher speed. Accordingly, a double data rate (DDR) SDRAM which inputs or outputs two data in one period of the external clock was developed. The DDR SDRAM continuously inputs or outputs two data through each data pin in synchronization with rising and falling edges in one period of the external clock. Therefore, a band width of the DDR SDRAM can be at least two times larger than that of the conventional SDR SDRAM without an increase of the clock frequency. The DDR SDRAM system thus can operate at the higher speed.
In further development, a prefetch is used to cope with a high speed operation of a DDR1/DDR2 SDRAM system. The prefetch is for reading and writing data corresponding to a burst length one of a single input or output command. For example, in case of a 2-bit prefetch in the DDR1 SDRAM, a minimum burst length becomes 2 bits. Accordingly, 2-bit data are input or output in one period of the external clock. For efficient data access, the semiconductor memory device inputs and outputs data in synchronization with rising and falling edges of the clock when exchanging the data with an external device. The device uses the 2-bit prefetch for processing in parallel two data in synchronization with one edge of the clock. In the DDR2 SDRAM, a 4-bit prefetch, wherein 4-bit data are read or written though each input/output pin concurrently, is implemented. A DDR3 SDRAM basically uses an 8-bit prefetch, when the burst length is 8-bits. However, the DDR3 SDRAM is designed to support both of the 4-bit and 8-bit prefetches.
The SDR SDRAM is provided with a mode register set (hereinafter, referred to MRS). The MRS stores information such as a burst type, a burst length, and a CAS latency for a variety of modes.
FIG. 1 is a block diagram of a DDR3 SDRAM in accordance with a conventional prefetch scheme.
As shown, the DDR3 SDRAM using 8-bit prefetch includes a bank BANK1 (the DDR3 SDRAM is provided with a plurality of banks but only one bank is described herein) and a column circuit unit group 10. The column circuit unit group 10 is provided with eight column circuit units 10A to 10H for 8-bit data, the maximum bit number of the prefetch. Meanwhile, a column control signal CCS is internally generated by a column access command CAC to enable the column circuit unit group 10 during a reading or writing operation of the DDR3 SDRAM.
FIG. 2 is a block diagram of the column circuit unit shown in FIG. 1.
Because the eight column circuit units 10A to 10H are composed of the same structure and operated in the response to the one column control signal CCS, one column circuit unit is described herein.
In detail, each of the column circuit units includes a data bus sense amplifier 24B, a column decoder 23B, a writing driver 25B, and a delay unit 22B. The data bus sense amplifier 24B amplifies data which are transferred from a cell to local input/output lines LIO and LIOB after sensing a voltage level of a bit line sense amplifier (not shown) during a reading operation. The column decoder 23B generates a signal YI to control a switch between the bit line sense amplifier and the local input/output lines based on an input address. Further, the writing driver 25B receives external input data during a writing operation. The delay unit 22B controls a timing of inputting the column control signal CCS to the data bus sense amplifier 24B, the column decoder 23B, and the writing driver 25B. Each of the column circuit units 10A to 10H performs an initial operation by the column control signal CCS generated internally when the column access command CAC for the reading or writing operation is input. Accordingly, each column circuit unit operates respectively and independently regardless of the operation of other column circuit units.
As described above, all column circuit units 10A to 10H start to operate in response to the column control signal CCS. Even though a burst length is 4 in the MSR, all column circuit units, i.e., the eight column circuits units, operate. Accordingly, the data bus sense amplifiers and the column decoders of all column circuit units operate in a reading operation, though not all output data are actually used. Unnecessary currents are consumed and power consumption is increased. In a writing operation, all column circuit units inclusive of unnecessary column circuit units also operate. If there is no data input, previous data latched on the local input/output lines LIO and LIOB can destroy data value in the cells.